搜索资源列表
cpu-kongzhi
- 1. 实现能够执行R型、LW、SW、BEQ以及J指令的单时钟控制器，使其能够支持基本的指令。 2. 用Verilog HDL实现单时钟CPU控制器，在ISE上进行波形仿真，并在FPGA上实现。-1. Implementations can perform R-type, LW, SW, BEQ, and J instruction every clock controller, to enable them to support the basic directives. 2 single-
SPI3_8bit
- 一整套通用的用Verilog代码实现的SPI3接口（8bit接口）协议代码，包含ISE工程文件，本代码在Xilinx公司的FPGA上实现，并且有Modelsim仿真的源文件-SPI3 verilog code（including ISE project and modelsim code)
dlx_verilog.rar
- 这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。,This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! T
seg7_lut_8_0.rar
- 七段阴极数码管的FPGA控制程序，开发平台为ISE或者quartus,Seven-Segment LED cathode the FPGA control procedures, development platform for the ISE or Quartus
FIFO
- 基于FPGA的FIFO控制器的设计与实现，ISE，verilog-FPGA-based design and implementation of FIFO controller, ISE, verilog
canbus
- CAN总线的FPGA实现，用Verilog编写，代码完整，而且有很完善的测试代码，用ISE直接打开，学习FPGA进阶的好项目-CAN Bus FPGA, written with Verilog, code integrity, but also very good test code, using ISE directly open, a good project to learn advanced FPGA
dds
- verilog 硬件语言实现DDS，使用ise11.1和modelsim se6.5仿真测试-verilog hardware language DDS, using the simulation test ise11.1 and modelsim se6.5
dpram
- FPGA实现双口RAM的工程文件，直接拿ISE打开即可，或者找里面的.VHD文件也可以-FPGA dual RAM
DOC-JTag-cable-drawing
- XILNX 的 JTAG 燒錄線內部電路圖. 已經驗証過可行, 配合 XILNX ISE 可直接對 FPGA 編程.-It s the circuit diagram of the XILNX JTAG programming cable. It was approved OK. Can drectly programming the FPGA via ISE platform.
all
- 基于FPGA的频率测试器的verilog HDL代码，测试范围1-10MHz，用XILINX公司的ISE软件打开。-Based on FPGA-frequency test the Verilog HDL code, test range 1-10MHz, with XILINX ISE software to open.
timer_0
- 计数器的FPGA控制程序，开发平台为ISE或者quartus-FPGA counter control procedures, development platform for the ISE or Quartus
io_lvds
- xilinx LVDS接口程序,xilinx LVDS接口程序-xilinx LVDS interface program,xilinx LVDS interface program
FPGADFPlabfiles
- 如何使用ISE和FPGA使用指南里面附带许多实验-How to use the ISE and FPGA UserGuide, which fringe much experimental
The_entire_FPGA_design_flow_Modelsim_Synplify.Pro_
- 详细的说明了FPGA设计的整个流程 FPGA设计全流程Modelsim>>Synplify.Pro>>ISE-Detailed descr iption of the FPGA design flow of the entire FPGA design flow full Modelsim> > Synplify.Pro> > ISE
serialcomuniactionsource_files
- 用于FPGA与232通信的编程设计，用VERILOG语言编写的，在ISE中仿真-232 communications for FPGA programming and design, using the VERILOG language in ISE Simulation
ISE_9.1i_quick_start_tutorial
- 简单易懂的Xilinx公司的专用FPGA编程软件快速入门教程-Quick Start Guide to the software of ISE of Xilinx
lvds
- 这是一个LVDS程序源文件，经过仿真正确。-this a LVDS source programme.
ise_book
- 关于xilinx的FPGA的EDK的程序（教程），使用ise集成环境-On the FPGA of the EDK program (tutorial), using ise integration environment
timer
- 用C语言实现在Xlinx公司的FPGA的延时程序在ISE软件编程环境下-With the C language implementation in the Xlinx the company' s FPGA-delay procedures in ISE software programming environments
FPGA_design_process
- FPGA 设计全流程：Modelsim>>Synplify.Pro>>ISE-FPGA design of the whole process: Modelsim>>Synplify.Pro>>ISE